module SCPU(
	input clk,
	input rst,
	input MIO_ready,
	input [31:0] Data_in,
	input [31:0] inst_in,
	output CPU_MIO,
	output MemRW,
	output [31:0] Addr_out,
	output [31:0] Data_out,
	output [31:0] PC_out,
	output [31:0] x0,
    output [31:0] ra,
    output [31:0] sp,
    output [31:0] gp,
    output [31:0] tp,
    output [31:0] t0,
    output [31:0] t1,
    output [31:0] t2,
    output [31:0] s0,
    output [31:0] s1,
    output [31:0] a0,
    output [31:0] a1,
    output [31:0] a2,
    output [31:0] a3,
    output [31:0] a4,
    output [31:0] a5,
    output [31:0] a6,
    output [31:0] a7,
    output [31:0] s2,
    output [31:0] s3,
    output [31:0] s4,
    output [31:0] s5,
    output [31:0] s6,
    output [31:0] s7,
    output [31:0] s8,
    output [31:0] s9,
    output [31:0] s10,
    output [31:0] s11,
    output [31:0] t3,
    output [31:0] t4,
    output [31:0] t5,
    output [31:0] t6
    );
    
    wire [1:0] ImmSel;
    wire ALUSrc_B;
    wire [1:0] MemtoReg;
    wire Jump;
    wire Branch;
    wire RegWrite;
    wire [2:0] ALU_Control;  
    
    SCPU_ctrl_0 U1(
		.OPcode(inst_in[6:2]), 
		.Fun3(inst_in[14:12]), 
		.Fun7(inst_in[30]), 
		.MIO_ready(MIO_ready), 
		.ImmSel(ImmSel), 
		.ALUSrc_B(ALUSrc_B), 
		.MemtoReg(MemtoReg), 
		.Jump(Jump), 
		.Branch(Branch), 
		.RegWrite(RegWrite), 
		.MemRW(MemRW), 
		.ALU_Control(ALU_Control), 
		.CPU_MIO(CPU_MIO)
  	);
    
    DataPath_0 U2(
    	.clk(clk), 
		.rst(rst), 
		.inst_field(inst_in), 
		.Data_in(Data_in), 
		.ALU_Control(ALU_Control), 
		.ImmSel(ImmSel), 
		.MemtoReg(MemtoReg), 
		.ALUSrc_B(ALUSrc_B), 
		.Jump(Jump), 
		.Branch(Branch), 
		.RegWrite(RegWrite), 
		.PC_out(PC_out), 
		.Data_out(Data_out), 
		.ALU_out(ALU_out),
		.x0(x0),
        .ra(ra),
        .sp(sp),
        .gp(gp),
        .tp(tp),
        .t0(t0),
        .t1(t1),
        .t2(t2),
        .s0(s0),
        .s1(s1),
        .a0(a0),
        .a1(a1),
        .a2(a2),
        .a3(a3),
        .a4(a4),
        .a5(a5),
        .a6(a6),
        .a7(a7),
        .s2(s2),
        .s3(s3),
        .s4(s4),
        .s5(s5),
        .s6(s6),
        .s7(s7),
        .s8(s8),
        .s9(s9),
        .s10(s10),
        .s11(s11),
        .t3(t3),
        .t4(t4),
        .t5(t5),
        .t6(t6)
  	);
endmodule